1. Field of the Invention
The present invention relates to an amplifier (hereinafter called “amp”) in a semiconductor integrated circuit, and to a step-down regulator which, by using the amp, outputs a constant voltage which is lower than a power source voltage, and to an operational amplifier (hereinafter called “operational amp”) using the amp.
2. Description of the Related Art
For example, the following documents and the like include disclosure of conventional techniques relating to an amp provided at a semiconductor integrated circuit, or a constant voltage power source circuit (voltage regulator) or step-down regulator or the like which uses the amp.
Japanese Patent Application Laid-Open (JP-A) No. 2003-330550
Japanese Patent Application Laid-Open (JP-A) No. 2004-118411
The technique of a constant voltage power source circuit is disclosed in JP-A No. 2003-330550. This constant voltage power source circuit has: an input stage amplifying circuit; an intermediate stage amplifying circuit which amplifies the output voltage of the input stage amplifying circuit; and an output stage amplifying circuit which amplifies the output voltage of the intermediate stage amplifying circuit. A bias circuit, which varies the bias current of the intermediate stage amplifying circuit proportionately to the output current of the output stage amplifying circuit, is provided within the intermediate stage amplifying circuit. In this way, even when a load whose fluctuations in consumed current are large is connected to the output terminal of the output stage amplifying circuit, the bias current of a transistor for driving within the intermediate stage amplifying circuit can be made to be small, and the capacity of a capacitor for phase compensation which is connected to the output terminal can be made to be small.
The technique of a voltage regulator is disclosed in JP-A No. 2004-118411. This voltage regulator has: a reference voltage source which outputs a reference voltage; a voltage dividing circuit which divides output voltage; a feedback voltage terminal to which a voltage obtained by dividing the output voltage is outputted; an error amp to which the reference voltage and voltage from the feedback voltage terminal are inputted; a first transistor connected in series between the voltage dividing circuit and the input power source voltage; and an overcurrent limiting circuit which receives output of the error amp, and outputs a signal that controls the first transistor. The overcurrent limiting circuit has a differential pair which receives a signal which is inputted to the error amp, and outputs the signal that controls the first transistor. Therefore, even when the input power source voltage and the output voltage are small (i.e., when the input/output voltage difference is small), the overcurrent limiting circuit operates and limits the increase in the output current and lowers the output voltage. A constant output voltage can thereby be outputted.
Further, as a conventional step-down regulator provided at a semiconductor integrated circuit, there is the structure shown in FIG. 6 for example.
FIG. 6 is a circuit diagram showing a structural example of a conventional step-down regulator.
This step-down regulator is structured by using an operational amp 10, and, on the basis of reference voltage VR, outputs a desired output voltage Vout, which is lower than a positive power source voltage (hereinafter called “VDD”) from an output terminal REGOUT. A large capacitor C1 for stabilization of from several to several 10 μF is connected between the output terminal REGOUT and the ground (hereinafter called “GND”). Therefore, the operational amp 10 is structured so as to not have a phase compensating capacitor for preventing oscillation.
The operational amp 10 is structured from an input stage amplifying circuit 10A, and an output stage amplifying circuit 10B connected to the output side thereof. The input stage amplifying circuit 10A has a current source 11 and an N-channel MOS transistor (hereinafter called “NMOS”) 12, and these are connected in series between the VDD node and the GND. An NMOS 13 for the current source, which together with the NMOS 12 structures a current mirror circuit, is connected to the NMOS 12. NMOS 14, 15 which structure a differential amplifying section, P-channel transistors (hereinafter called “PMOS”) 16, 17 which structure a current mirror circuit, and the VDD node are connected in series to the NMOS 13. The reference voltage VR is inputted to the gate of the NMOS 15.
The output stage amplifying circuit 10B has a PMOS 18 for output, the output terminal REGOUT, and an NMOS 19, and these are connected in series between the VDD node and the GND. The PMOS 18 is an output transistor which is gate-controlled by the drain of the NMOS 15 and the drain of the PMOS 17. The NMOS 19, together with the NMOS 12, 13, structures a current mirror circuit. A voltage-dividing circuit, which is structured from voltage-dividing resistors 21, 22, is connected between the output terminal REGOUT and the GND. The divided voltage is feedback-inputted to the gate of the NMOS 14.
In the step-down regulator of this structure, in a case in which the output voltage Vout fluctuates due to fluctuations in the load connected to the output terminal REGOUT, the amount of fluctuation is detected by the voltage-dividing resistors 21, 22, and the detected voltage is feedback-inputted to the gate of the NMOS 14 of the differential amplifying section. The difference between the reference voltage VR and the detected voltage is amplified by the NMOS 14, 15 of the differential amplifying section. The NMOS 18 is gate-controlled by the amplified voltage, and the output voltage Vout on the output terminal REGOUT is controlled to a constant voltage.
However, there are the following problems (a) through (c) with the conventional step-down regulator.
(a) In the conventional step-down regulator, phase compensation is carried out in accordance with the capacitance value of the capacitor C1 which is connected to the output terminal REGOUT. Therefore, if the capacitance value of the capacitor C1 is made to be small, the phase margin becomes small, and there is the problem that oscillation occurs.
(b) At the time of the start of operation of the step-down regulator, due to the rush current (overcurrent) to the capacitor C1 which is connected to the output terminal REGOUT, the voltage greatly exceeds (overshoots) the constant voltage, and thereafter, stabilizes at the constant voltage. Therefore, there are the problems that the circuit elements deteriorate due to this overcurrent, the time from the overshooting until the stabilization at the constant voltage is long, and the rise at the time of start of operation is slow.
(c) In order to overcome above-described problems (a), (b), it has been thought to use the technique disclosed in JP-A No. 2003-330550 or JP-A No. 2004-118411.
For example, it can be thought to provide the intermediate stage amplifying circuit, which has a bias circuit and is disclosed in JP-A No. 2003-330550, between the input stage amplifying circuit 10A and the output stage amplifying circuit 10B, and to vary the bias current of the transistor for driving within the intermediate stage amplifying circuit proportionately to the output current of the output stage amplifying circuit 10B by this bias circuit, and control the gate voltage of the PMOS 18 for output. However, the doubt remains as to whether or not the phase margin can be improved (i.e., the capacitance value of the capacitor C1 can be made small) without adversely affecting the other circuit portions, and even if it were possible to make the capacitance value of the capacitor C1 small, the prevention of overcurrent, which is the problem of above-described (b), could not be achieved.
In order to achieve prevention of overcurrent, it can be thought to use the technique of the overcurrent limiting circuit disclosed in JP-A No. 2004-118411. However, JP-A No. 2004-118411 does not have a technique relating to phase compensation, and has a different circuit structure than JP-A No. 2003-330550 and the technique of FIG. 6. Therefore, combining the technique of the overcurrent limiting circuit disclosed in JP-A No. 2004-118411 with JP-A No. 2003-330550 or the circuit of FIG. 6 is itself technically impossible. It is difficult to achieve prevention of overcurrent without uselessly complicating the circuit structure, and further, without increasing the scale of the circuit.